1. Field of the Invention
The present invention relates in general to a memory system for processing a digital video signal, and more particularly, to a memory system for processing a digital video signal capable of accessing block data in an integer pel mode or half pel mode.
2. Discussion of the Related Act
Generally, random access memory RAM such as dynamic random access memory DRAM or static random access memory SRAM is used as the memory device of a memory system for processing digital video signals. In addition to RAM, a bit stream buffer and a memory controller are also required to convert a format of data in a format of block unit.
Here, the image processing system utilizing the video signal processing memory, determines motion vector data between the previous screen and current screen for compressing the data, and then propagates the image in response to the amount of the motion vector. The receiver processes the signal by using this to revive an original image. The image of motion vector data is processed by macro block units of 16.times.16 bits.
As illustrated in FIG. 1, the conventional memory system for processing digital video signal is described in U.S. Pat. No. 5,430,684 filed by the same applicant, and incorporated by reference herein.
Referring to FIG. 1, the conventional memory system for processing digital video signal includes a random block access RBA control unit 10 for controlling the random block access using signals externally applied. An address generator unit 20 generates an address using an initial address in accordance with the control of the RBA control unit 10. A memory cell array 30 stores data in accordance with the control of the RBA control unit 10 and the address generator unit 20. Transmission control unit 40 controls the data transmission of the memory cell array 30 in accordance with the RBA control unit 10 and the address generator unit 20. An input/output device inputs and outputs data in accordance with the control of the RBA control unit 10 and transmission control unit 40.
The address generator unit 20 includes a row address generator 21 and a column address generator 22. The transmission control unit 40 includes an RBA selector 41, a serial register 42, and an RBA Y-decoder 43. The input/output device 50 is includes an input/output unit 51 and an input/output controller 52.
As illustrated in FIG. 2, the RBA control unit 10 includes an X-state pointer part 11 for receiving a serial clock SC, RBA mode flag signal RBAM, RBA state pointer enable signal RSPE, and Y-state pointer signal YRn, and then outputting an X-state pointer signal Xrn. An Y-state pointer part 12 receives RBA mode flag signal RBAM, RBA state pointer enable signal RSPE, and serial clock SC, and then outputs a Y-state pointer signal Yrn. An internal row address strobe RAS generator 13 generates an internal RAS signal /RASi by using an external row address strobe signal /RAS, the X-state pointer signal XRn, the Y-state pointer signal YRn, and the RBA mode flag signal RBAM. An internal column address strobe CAS generator 14 generates an internal CAS signal /CASi by using an external CAS signal /CAS, XRn, YRn, and RBAM. A transmission controller 15 outputs a transmission signal XF, register enable signal RGE, and serial decoder enable signal SDE by using the YRn, RBAM, and SC. A reading/writing controller 16 receives the RBAM, a write enable latch signal /WEL, XRn, and YRn, and then outputs an RBA writing X-enable signal RWXE, RBA-state pointer enable signal RSPE and RBA Y-enable signal RYE. A mode selector 17 receives the XRn, YRn, an external data transmission signal /DT, RBA control signal RBA and a write enable signal /WE, and then outputs RBAM and /WEL. An internal clock generator 18 generates a system block SYCK by using RBAM, RYE, and SC.
Hereinafter, the operation of the memory system for processing digital video signals will be briefly described.
When the row address strobe signal /RAS falls, the memory system sets a proper mode in accordance with the state of the write enable signal /WE, data transmission signal /DT, and RBA control signal RBA, and forms a row address for selecting word lines of the memory cell array 30, utilizing an initial row address of the block applied to an address input pad AI.
When the column address strobe signal /CAS also falls, the memory system selects a proper cell of memory cells connected to a selected word line of the memory cell array 30, utilizing an initial column address of the block which is applied to the address input pad AI. Then the memory system forms a selection signal SELn for controlling the data transmission between the selected cells and the serial register 42 and an internal Y-address for connecting the data line of input/output part 52 and that of the serial register 42. The input/output data (16.times.16 bits) of any block is then continuously input/output through the input/output unit 51 in accordance with the control of the input/output controller 52. This operation is repeatedly performed to read and write block data.
For a reading operation, it is possible to give the initial address of the block of 16.times.16 bits as an initial address of a random position in the memory cell. However, for a writing operation, only an address whose initial address is a multiple of 16 can be input therein. That is, the system operates as a random block access for a reading operation, and a serial block access for a writing operation.
Meanwhile, in international standards for processing digital signals such as MPEG2 or HDTV, the motion vector of a macro block is displayed by a half pel unit for improving the resolution, and specifically, the macro block size of 17.times.17 bits is required therefor.
But, the conventional memory system for processing digital video signal sets its block size to 16.times.16 bits for a reading operation, and thus the system is only used for displaying the motion vector of integer pel. As a result, the conventional system can not access the block size of half pel unit, and therefore is not suitable to naturally process the resolution of current video data.